In recent years, significantly high data transfer rate is required for data transfer between semiconductor devices (between CPUs and memories for example). To accomplish high data transfer rate, the amplitude of input/output signals is increasingly reduced. If the input/output signals have reduced amplitudes, the desired accuracy of impedances of output buffers becomes severe.
The impedance of the output buffer varies depending on process conditions during the manufacturing. Also, during its actual use, the impedance of the output buffer is affected by variations in ambient temperature and power source voltage. When high impedance accuracy is required for the output buffer, output buffers that can adjust their impedances are utilized (Japanese Patent Application Laid-open Nos. 2002-152032, 2004-32070, 2006-203405, and 2005-159702). The impedance of such an output buffer is adjusted by circuits generally called “calibration circuits”.
As disclosed in Japanese Patent Application Laid-open Nos. 2006-203405, and 2005-159702, the calibration circuit includes a replica buffer with the same configuration as the output buffer. When a calibration operation is performed, with an external resistor connected to a calibration terminal, the voltage of the calibration terminal is compared to the reference voltage and the impedance of the replica buffer is adjusted accordingly. The result of adjustment of the replica buffer is then reflected in the output buffer, and the impedance of the output buffer is thus set to the desired value.
As described above, in the calibration operation, a voltage appearing in the calibration terminal on the chip is compared with the reference voltage. However, the external resistor used in the calibration operation is connected to the external terminal on the package. Therefore, the impedance of the replica buffer does not necessarily coincide with the impedance of the external resistor. In other words, a certain level of resistance component is present between the calibration terminal on the chip and the external terminal on the package. Therefore, the impedance of the replica buffer is slightly deviated from a desired value, because the sum of the resistance value of the external resistor and the resistance component on the package becomes a target value.